My idea as of now is to store values in external RAM (with mif file) and on startup latch values from RAM into each variable (hoping there's enough memory bits) + Zd, then that's not really feasible to do in one clock tick, you'd have to pipeline it and do it over multiple ticks. ![]() However if you want to do something like Ad + Bd + Cd +. ![]() ![]() Now if two accesses per tick isn't good enough, you can start being clever and initialising multiple BRAMs separately and either store independant data sets in each or duplicate your data, this would let you increase the amount of accesses per tick. BRAMs also support dual port mode (read up on this in the Device Handbook for your FPGA to understand the different modes and how they utilise the BRAMs), which lets you access two addresses per tick. ![]() However you can only access one from a BRAM per clock tick, and they have a 1 - 3 tick latency, it's pipelined though so you can have 1 read per tick bandwidth. FPGAs contain BRAM (block RAM) hardware blocks that are designed for storing data like this.
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